The invention is generally related to digital filters, and more particularly, to finite impulse response (FIR) filters and the hardware implementations thereof.
Digital filters such as finite impulse response (FIR) filters are used in a number of electronic applications. For example, digital filters are used extensively in wireless communications applications, e.g., in wireless telephone handsets, wireless network hardware, and the like to filter and process incoming wireless signals to recover a data stream therefrom. Typically, but not exclusively, digital filters are implemented on integrated circuit devices along with other control and digital signal processing circuitry.
A digital filter is often required to handle data at a relatively high rate, and as a result, it is often desirable to minimize the internal delays within a digital filter. Moreover, given the constant drive toward miniaturization, it is often desirable for a digital filter to be as compact and occupy as little space as possible on an integrated circuit device. Furthermore, when used in portable applications such as wireless telephone handsets, it is often desirable to minimize the power consumption of a digital filter to assist in extending the overall battery life of a device.
One commonly-used type of digital filter is an finite impulse response (FIR) filter, which has a behavior (in the time domain) generally represented by the equation:                               y          ⁡                      [            k            ]                          =                              ∑                          i              =              0                                      n              -              1                                ⁢                      xe2x80x83                    ⁢                                    x              ⁡                              [                                  k                  -                  i                                ]                                      xc3x97                          H              ⁡                              [                i                ]                                                                        (        1        )            
where n is the number of coefficients, x[k] is the input value at the k-th time step, H[i] is a signed integer FIR filter coefficient, and y[k] is the filtered output value for the filter at the k-th time step.
To implement such a transmission function in hardware, typically separate multiplier and summation stages are utilized, with the multiplier stage configured to generate the product of each input value and filter coefficient, and the summation stage configured to sum the products generated by the multiplier stage to generate a filtered output. In some applications, the multiplier stage is configured to perform each multiplication in parallel using parallel circuitry; however, such parallel circuitry is often too large for a number of space constrained applications. Another approach is to utilize a single multiplier that is sequentially provided with input values and coefficients to generate products to be summed by the summation stage.
Despite advancements in the optimization of multiplier structures (e.g., the Booth-Wallace multiplier design), often the multiplier stage is still the largest and slowest component of an FIR filter. Attempts to reduce the size, power consumption and delay associated with a filter design therefore often focus on reductions to the multiplier stage of the filter.
One manner of reducing the size of a multiplier is to decrease the resolution (or number of bits) of the digital values used to represent the ideal filter coefficients. However, whenever the resolution is decreased, the response of the filter (i.e., the degree to which the actual filter transformation function matches the ideal transmission function for which the filter is designed) also decreases due to increases in the truncation errors that result from rounding and converting the ideal filter coefficients into fixed width digital values. Consequently, the degree in which the resolution of the coefficients can be decreased is often limited by the necessary tolerance range of the filter.
Other approaches attempt to avoid the use multipliers by a manipulation of the FIR filter coefficients. As one example, coefficients may be required to equal an integral power of two, such that multiplication may be performed using a simple and efficient shift register design. As another example, configurable blocks of adders and shift registers may be used to essentially represent each coefficient as a sum of integral powers of two such that multiple shift operations may be performed in parallel on an input value to represent the multiplication of the input value by a coefficient (e.g., multiplication by a coefficient with a value of 10 could be implemented by summing together the results of two shift operations corresponding respectively to multiplication of an input value by 8 and 2).
Each of these approaches, however, can significantly reduce coefficient resolution, requiring additional coefficients to maintain adequate filter response. As a result, additional circuitry is required to handle the additional coefficients, increasing space, power consumption and delay for the filter. Moreover, often the layout of such multiplier alternatives is more difficult and complex than for a multiplier, and the resulting circuit layout is not as efficient. A number of multiplier designs have been highly optimized for compactness, low power consumption and speed, and as a result, the gains associated with such alternate structures over an optimized multiplier are negligible, if at all. In addition, any improvements in size reduction afforded by such alternate structures is often offset by increased delays, making such structures unsuitable for a number of high speed applications.
Therefore, a significant need exists in the art for an improved digital filter design that provides a desirable filter response in less space, with less power, and with less delay than conventional designs.
The invention addresses these and other problems associated with the prior art by providing a circuit arrangement and method in which a multiplier stage of a digital filter utilizes a programmable shifter coupled downstream of a multiplier to shift the product of an input value and a xe2x80x9cpre-scaledxe2x80x9d filter coefficient that implements a predetermined filter function. Through the judicious selection of an appropriate pre-scaled filter coefficient and a xe2x80x9cshift distancexe2x80x9d to shift the product, truncation errors associated with a digital implementation of a filter may be minimized, offering improved filter response compared to other filter implementations with like coefficient resolution, or in the alternative, permitting suitable filter response to be maintained with reduced coefficient resolution. Moreover, where the coefficient resolution is reduced, a filter may be implemented using relatively less space, less power consumption and less delay than in comparable conventional designs.
A pre-scaled filter coefficient consistent with the invention may be used to represent an ideal filter coefficient from a filter function in a number of manners. A pre-scaled filter coefficient may be derived from an ideal filter coefficient through scaling of the ideal filter coefficient by a scaling factor equal to two to the power of the shift distance associated with the pre-scaled filter coefficient. As such, the scaling operation that is inherent in the pre-scaled filter coefficient is negated by the shift operation performed by the programmable shifter.
A pre-scaled filter coefficient may also be derived from an ideal filter coefficient through a rounding operation performed on the product of the ideal filter coefficient and the scaling factor. Furthermore, a pre-scaled filter coefficient may be derived from an ideal filter coefficient through the addition of a correction term to the rounded product of the ideal filter coefficient and the scaling factor. Through the addition of a correction term, often further improvements in filter response can be obtained above and beyond those provided by scaling by a scaling factor.
In general, it will be appreciated that a number of operations may be performed to generate various pre-scaled filter coefficient representations consistent with the invention. Therefore, the invention is not limited to the particular implementations discussed herein.